This invention relates to a semiconductor device, in which a trench is formed in a semiconductor substrate with a layered film formed on an inner wall of the trench, and to a method for manufacturing the same.
U.S. Pat. No. 5,321,289 (which corresponds to Japanese unexamined patent publication JP-A-6-132539) discloses such a transistor, as shown in FIG. 20, having a trench-gate structure in which a trench is formed on a semiconductor substrate and a gate insulating film composed of an oxide film and a nitride film is formed on an inner wall of the trench. Because the gate insulating film is composed of a compound film of the oxide film and the nitride film, the device can provide a higher gate withstand voltage and a lower on-voltage than a device in which the gate insulating film is composed of only an oxide film.
As a result of studies of the semiconductor device described above, however, it was found that electric field tends to concentrate on corner portions of the upper and bottom portions of the trench, which lowers the withstand voltage. Further, the gate insulating film composed of the oxide film and the nitride film has many interface states. In this connection, it was further found that a threshold voltage was liable to vary due to effects of the interface states at a transistor operation state. This can lower the reliability of the device.